Electrically-erasable, programmable read-only memories (EEPROMS) employing single transistor memory cells (also referred to as bits), and which use hot carrier injection for programming and Fowler-Nordheim tunneling for erasure are in wide usage, and have been described, for example, in "A Single Transistor EEPROM Bit and Its Implementation in a 512K CMOS EEPROM(s)," Mukheree, et al., XEDM 1985, pp. 616-619, and "A 90 NS 100K Erase/Program Cycle Megabit Flash Memory," V. Kynett, et al., ISSCC 1989, pp. 140-141.
Such EEPROMs are programmed via hot-electron injection to a floating gate by the application of a high voltage to the control gate and drain of a particular memory bit while keeping the source of that memory bit grounded. For example, the drain programming voltage, V.sub.dp is kept below 6.5 volts while the control gate programming voltage, V.sub.cgp is held at 12 volts. Erasing is accomplished by applying a relatively high voltage across the control gate and source, while floating the drain. In typical EEPROMS, erasing is accomplished by maintaining the control gate voltage at V.sub.cgo =.theta. volts, and raising the source to V.sub.se =12 volts. With flash EEPROMs, memory cells are divided into sectors. Within each sector, the sources of all of the memory cells are coupled to a common node. Thus, erasure in typical flash EEPROMs is on a sector by sector basis.
Memory cells in flash EEPROMs are N-type metal oxide semiconductor field effect transistors. Thus, N-type drains and sources are implanted in a P-type substrate. With standard erasing as described above, source to substrate current can be relatively high, due to source to substrate breakdown, since the substrate is typically held at zero volts. The magnitude of this substrate current increases as the number of memory cells within particular sectors increases, since all of the memory cells within a particular sector are erased at once. Because of this high current, which may be as high as ten milliamps in a one megabyte flash EEPROM chip, external power supplies are required to generate enough current at the higher voltages required for flash erasure. The requirement for such power supplies is unattractive, and thus flash EEPROMs without such a requirement are needed.
To avoid the substrate current problems described above, flash EEPROMs have been proposed in which erasing is accomplished by pulling the control gates negative with respect to the source voltage. For example, the source is held at zero volts while the control gates are lowered to minus sixteen volts. With the substrate also at zero volts, the substrate current problem is avoided. Another example pulls the control gate down to minus eleven volts, raises the source to five volts, and allows the drain to float, thus eliminating the need for a positive twelve volt power supply. Such circuits present the possibility of erasure down to a single wordline. However, circuits that allow for these negative voltages have not been able to decode many wordlines efficiently, without the use of triple well processes which result in process complexity.
Therefore, a need has arisen for a flash EEPROM which allows for negative voltage wordline decoding, and which allows for wordline decoding down to a single wordline.